Power 7 Roundup

I was at the Power 7 Champions pre-briefing in Austin Tx Jan 11th week and, now that its official, have the following to report for you. I’ll focus on HW in this blog entry, and cover software as we move forward.

 

HARDWARE.

2010 will be a year when major computer systems vendors trot out the newest 8 core per socket computer chips and tout vastly increased performance, energy profiles and workload optimization.  Presumably they will boast about how much better their chip is than the competitors while convincing installed base to upgrade in order to scale and become more energy efficient. Interestingly, far fewer vendors will legitimately remain in this race:  Sun Microsystems is an uncertain state and, HP’s “Tukwilla”, (essentially refreshed Itanium )is as doomed as the (T)itanic. This leaved two clear front runners, IBM and POWER 7 and Intel with Nehalem EX.

 IBM’s Power 7 has jaw-dropping technical specifications and compares to Power 6 in the following way:

 POWER7 has 8 cores per chip vs 2 on POWER6. It can also run  with 6 cores or 4 cores in “turbo” mode. Turbo shuts down 4 of 8 cores and, increases the clock speed while sharing the L3 cache slicing the “pie” amongst fewer cores (more cache/core)..

  • 45nm vs 60nm technology. The POWER7 lithography size continues to shrink and takes advantage of IBM patented used Cu, SOI, eDRAM technology
  • 567mm2 vs 341mm2 size. The physical chip size is less than twice as big considering it includes 8 cores and the L3 cache.
  • eDRAM: greater density – 1/3 space of 6T SRAM, less power requirement – 1/5 standby pwer, better performance – 6:1 latency improvement for L3 access vs external, greater bandwidth- 2X on chip interconnect
  • Transistors: 1.2B vs 790M (functional equivalency of 2.7B) P6 due to efficiency of eDRAM transistor: data ratio. This resulted in savings of 1.5B transistors and enables L3 to go on chip. Furthermore eDRAM has 250X better soft error rate than DRAM provides better RAS.
  • 3.0 to 4.1 .Average clock speeds are lower, saving energy/heat while delivering equal or better per core performance
  • L2 256 KB/Core vs 4MB/core. L2 cache design is completely overhauled due to L3 on-chip. The savings in size/transistors is leveraged by L3.
  • L3 32MB on chip vs 32MB off chip L3 cache. Breakthrough both in throughput and #transistors delivers 6:1 latency improvement over external L3. Allows for dramatic reduction in required L2 cache and results in  2x bandwidth improvement
  • 4 way SMT per core vs 2-way on Power 6  results in net 32 threads/chip. This is twice threads per core and 8* threads per chip.
  • Memory controller:  100GB/s memory bandwidth 100GB/sec per chip
  • Up to 32 sockets with 360 GB/s SMP bandwidth/chip
  • LPARS 10/core: the same LPAR per ratio is maintained but upper limit is moved to 1000 LPAR per top system
  • Out of Order execution. P6 went back to in-order to save transistors but with new efficiency, Out Of Order is back in and means systems can run faster.
  • New Power Bus for GX throughput
  • 4th Gen SMP Fabric bus as distributed switch

 Net: 4X performance, t 3X performance/watt of POWER6 servers. More than doubles performance per core from POWER5 and better than POWER6 . When used in TurboCore mode: 1.5X P6 performance per chip.

 A look at the new models to be announced (Hi End and Low end to come later in the year)

 Model  750: 4u (Energy Star Compliant)

4 sockets with

    • 6 cores @ 3.3 or
    • 8 cores @ 3.0, 3.3, 3.55

Contrasted to the Model  550 it replaces:

  • 24 core (4 sockets)  vs. 8 core
  • 512 GB memory vs.  256 on 32DIMM slots
  • 8 SFF DASD (no 3.5”)

 

Model  755: 4u … new market – low end HPC cluster node

  • 4 socket 32 Core HPC node @ 3.3GHz Energy Star compliant
  • 2-Port infiniband 12X DDR
  • Certified with IBM HPC software stack
  • AIX , Linux (no i)

Model  770: 4u

  • Up to 4 enclosure including 2 sockets each with
    • 6 cores @ 3.55 or
    • 8 cores @ 3.1 . Energy Star compliant

Contrasted to the Model 570 it replaces, (all new design)

  • 16 core per enclosure vs 8 core per enclosure max
  • 512 GB memory vs 192
  • All PCIe

Model  780: Seems to fit in a special IBM 19” cabinet

  • Up to 4 enclosures including 2 sockets each with
    • 4 cores @ 4.1GHz TurboCore  or
    • 8 cores @ 3.8 GHz

 

Blades:

  • PS700 – 4core single socket
  • Ps701 – 8 core single socket
  • PS702  16 core double sized

            Editorial

You may need to do a double take on these facts: How can the per core performance improve while clock speeds are reduced? Simply, lower latencies and twice the threads per cores.

How can the energy envelope for 8 way be similar to 2 way (up4 X efficiency?). For this, the IBM processor engineers deserve the credit. First, this is impacted by lowering the number of transistors/per c ore and second by using sensible clock speeds. If you keep in mind that the energy use increases at log scale as processors reach maximum frequency, the solution to “turn down” clock speeds in order to save power makes sense and also sets the stage for “turbo mode” which we described. Customer vying to save software licences by maximizing performance/core (Oracle) can take advantage of this feature. Customers who may pay per user (SAP) may prefer the more efficient and scalable standard mode.

How will this compare to Nehalem?

On the surface, similarities between the chips are obvious. IBM is quite afraid of this baby. It pays to point out the finer detail and big impact.

  • 2 thread vs. 4 thread per core – Highly threaded should get double performance.
  • 10-20% overheads for VMWare and other virtualization on Nehalem based on benchmark publication bare metal vs. VMWare. IBM says all their benchmark results are from virtualized systems.
  • 60% vs 80% optimal workload utilization factor vs 40-60. Expect higher utilization

Better SMP and horizontal scalability with POWER.

IBM officially says POWER7 is targeted to the following markets:

  • Accelerate Migrations from Sun, HP and other UNIX Markets (sized at $8B)
  • Consolidate workloads from Intel/Windows/Linux/Solaris to Power (sized at $30B)
  • Protect base and minimize leakage to Nehalem

My take is that the POWER processors and systems announced will have value to customers who genuinely care about performance, scalability and RAS. In other words, for a small shop looking at a low cost for a 4 u desk side server who can’t fathom needing more than  cores to run their system. Big customer may eat this stuff up but for SMB-sized… we need to keep in tune with Smart Business.

HMC Update:

Polaris is the codeword for project to  Integrate HMC & IVM Functionality with Systems Director.

All configuration, service and management capabilities provided by the HMC and IVM today will be supported natively in IBM Systems Director (with some minor exceptions). IBM System Director will be the primary platform management tool for newer hardware.

Polaris is the next generation Hardware Management Console (HMC) combining:

  • The functionality of the HMC
  • The simplicity of the Integrated Virtualization Manager (IVM).
  • The value-add function of Systems Director

Polaris will be delivered as a Systems Director Appliance (both Physical and Virtual). 

Polaris will support P6 and P7 hardware (including blades). The virtual implementation will be targeted to VMWare and KVM virtual image.

I sense good education and consulting opportunity to transition customers to Director.

Active Memory Expansion Model 770 780

There was plenty talk about this. It’s a way to use “spare” CPU cycles to effectively give more memory capacity to the partition using compression / decompression of the contents in true memory

Interested in more. Come to our MoM on Jan 17th at IBM Canada Lab!

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One Response

  1. This is the 4th blog, of your site I checked out. Yet I personally love this particular one, “Power 7 Roundup TEC
    2010” the most. Regards -Ermelinda

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